Contact Information

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    Chhend Colony , Rourkela, Orissa 769004, India
  • call
    (0661) 2482556
  • mail_outline
    (0661) 2482562
  • email
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  • Approved By: UGC AICTE

M.Tech. (VLSI Design & Embedded System)


Duration:

2 Years

Eligibility:

Graduation

Course Duration: Two Year (Semester  System)

Course Eligibility : B.E./B.Tech. with at least 50 % marks or Equivqlent CGPA

Admission Criteria: Merit in qualifying examination, subject to eligibility criteria.

Entrance/Eligibility Test: As per University Rules

Programme Mode: Regular

Course Syllabus

Semester-I     

Course Code

Course Title

VLPC101

HDL and High Level Synthesis

VLPC102

Digital Integrated Circuit Design

VLPC103

Semiconductor Device Modeling and Simulation

 

Electives – I (any one)

VLPE101

VLSI Fabrication Technology

VLPE102

VLSI Digital Signal Processing Systems

VLPE103

VLSI Testing

 

Electives – II (any one)

VLPE104

Analogue Integrated Circuit Design

VLPE105

VLSI Physical Design

VLPE106

Reliability and Testability of IC Design

VLPR101

EDA Lab

VLPT101

Seminar on Pre-thesis work-1

 

Semester-II

VLPC201

Embedded System Design

VLPC202

RF and Mixed-Signal Integrated Circuits

(any one)


VLPE201

Microsystems – Principles, Design and Application

VLPE202

Analogue and Mixed-Signal Testing

VLPE203

VLSI and MEMS Packaging

VLPE204

ASIC and SoC Design

EL-4(any one)


VLPE205

Low Power Digital VLSI Design

VLPE206

 Emerging Topics in IC Design

VLPE207

Introduction to Nanoelectronics

EL-5(any one)


VLPE208

Statistical Signal Processing

VLPE209

Statistical Signal Processing

VLPR201

Embedded System Lab

VLPT201

Seminar on Pre-thesis work-2

VLCV201

Comprehensive Viva-Voce - I

 

Semester-III

OpenElective (any one)

Project Management/Project Costing/Technology Management/ Research Methodology/ Optimization Techniques/Computational Intelligence

Thesis-1

Thesis – I

 

Semester-IV

VLPT401

Thesis – II

VLCV401

Seminar

VLCV402

Comprehensive Viva-Voce – II