Mewar University - MU Courses

M.Tech. (VLSI Design)

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Duration: 2 Years

Eligibility: Graduation

Eligibility Conditions:

A candidate for being eligible for admission to the Master of Technology in VLSI Design in the faculty of engineering and technology should have passed B.Sc. (Engg.)/B.Tech/B.E. or any other equivalent degree in the relevant discipline/branch from any recognized Indian or foreign University.

A candidate should have at least 55% marks or equivalent CGPA in the qualifying examination (50% marks or equivalent CGPA for Scheduled Caste/Scheduled Tribes Candidates) on the basis of which the admission is being sought.

Overview of the Programme: The normal duration of programme shall be four Semesters for regular students. However, in exceptional circumstances, only dissertation work may be extended and has to be completed within five years from the date of enrolment for this programme. This extension requires the prior approval of the Vice-Chancellor of the University.

The complete programme comprises of 12 theory courses (08 Core and 04 elective) and 02 Lab courses followed by a seminar and the research/ project work in the form of a dissertation. Student has to obtain at least 40 % marks to pass the examination (both internal and external examination separately) for all the courses specified in the scheme of the programme. The degree will be awarded on the basis of cumulative marks obtained in all the four semesters and the division obtained will be as under:

Course Structure

Course Code	Course Title
Semester - I
VD-611	Semiconductor Device Modelling
VD-613	Digital IC Design
VD-615	Embedded Systems
VD-711/713/715	Elective-I
VD-721/723/725	Elective-II
VD-617	Digital Design Lab
Semester - II
VD-612	HDLs and FPGAS
VD-614	Analog IC Design
VD-616	Digital   Signal  Processing and DSP Architectures
VD-712/714/716	Elective-III
VD-722/724/726	Elective-IV
VD-618	Analog Design Lab
Semester - III
VD-621	Digital system Testing & Testable Design
VD-623	Optimization Techniques
VD-625	Seminar
Semester - IV
VD-628	Dissertation
List of Elective - I
VD-711	Asynchronous System Design
VD-713	Low-Power VLSI Design
VD-715	Memory Design and Testing
List of Elective - II
VD-712	RF Integrated Circuits
VD-714	Advanced Computational Methods
VD-716	FPGA Based System Design
List of Elective - III
VD-721	Mixed Signal IC Design
VD-723	Advanced Computer Architecture
VD-725	Neural Networks
List of Elective - IV
VD-722	Micro Electro Mechanical Systems
VD-724	VLSI For Wireless Communication
VD-726	Research Methodology

Course Detail

Semester - I

VD-611 Semiconductor Devices Modelling

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Brief review of silicon devices & fabrication processes, Recent developments in icroelectronic devices.

p-n junction- current flow mechanisms , DC , small signal, transient model under forward and reverse bias conditions, circuit models for different types of p-n junction diodes.

Bipolar junction transistor-current flow in BJT’s, charge control models for BJT’s, DC and small signal equivalent circuits, Gummel Poon mode, MEXTRAM model, HICUM model, second order effects- effects of non-uniform doping in the base, high injection, heavy doping effects in emitter, emitter crowding , non conventional BJT’s- poly silicon emitter transistor, HBT.

MOSFETs: modeling of weak and strong inversion in three terminal and four terminal MOS transistors, effect of small dimensions- DIBL, charge sharing, channel length modulation, hot carrier effects. Small signal models of MOSFETs for low and medium frequencies, large signal modeling of MOS transistor in dynamic operation. Level 1, 2, 3, 4(BSIM) models, HSPICE Level 50 model.

Modeling for circuit simulation: types of models combining several effects into one physical model, parameter extraction, properties of good models

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-613 Digital IC Design

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Modeling of Interconnects: Interconnect parameters, wire models, SPICE models for wires. CMOS Inverter: Static and Dynamic Behavior, Power, Energy and Energy Delay, Technology scaling and its impact.

Design of CMOS Combinational Logic Gates: Static and dynamic CMOS Design, Speed and power dissipation in dynamic circuits, cascading of gates, designing logic for reduced supply voltages, simulation of logic circuits.

Design of CMOS Sequential Logic Circuits: Static and dynamic latches and registers, alternative register styles, pipelined sequential circuits, non-bistable sequential circuits.

Custom, Semi-custom, and Structured array design approaches: Cell Based Design – standard, compiled , macro cells, mega cells, ArrayBased Design – mask programmable and rewired arrays.

Coupling with Interconnects: Effects of Interconnect Parasitics, Advanced Interconnect techniques.

Timing issues in Digital Circuits: Timing classification, synchronous timing basics, sources of skew and jitter, clock distribution techniques, latch-based clocking, Self-timed circuit design, synchronizers and arbiters, clock synchronization using PLL.

Design of ALU- a case study: data paths, adder, multiplier, shifter, power and speed trade-off in data path structures, power management.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-615 Embedded System Design

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Introduction: Embedded Systems and Architectures. System integration, ardware/Software Partitioning, Design Considerations and Trade-offs, Structural and behavioral descriptions.

Processors: ARM and SHARC processors- processor and memory organization, data operations, flow of control, input and output devices and primitives, busy-wait I/O, interrupts, supervisor mode, exceptions, traps. Memories: Caches, MMUs and address translation; CPU Performance: pipelining, super scaling execution, caching, CPU power consumption.

Interfaces and Communication Mediums: Bus protocols, DMA, system bus configurations, ARM Bus, SHARC Bus, Memory Devices- organization and types, I/O Devices-timers and counters, ADC and DACs, keyboards, LEDs, Displays and touch screens , Interfacings-memory and device interfacing. Designing with microprocessors.

Programming an Embedded System: Program design patterns for embedded systems, data flow and control/data flow graphs,analysis and optimization of execution time, energy, power, and program size. Processes: multiple tasks and processes, context switching, Operating Systems: Process state and Scheduling, O.S. structure, timing requirements on processes, interprocess communication and mechanisms.

Examples and Case Studies.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

Practicals

VD-617 Digital Design Lab 

Laboratory Experiments:

• Design and simulation of 8-bit SISO and SIPO type registers modeled in VHDL and VERILOG, and synthesis on FPGA.
• Circuit simulation of CMOS Inverter - study of static and dynamic behavior.
• Design and simulation of 8-bit PISO and PIPO type registers modeled in VHDL and VERILOG, and synthesis on FPGA.
• Study of the effect of variation in VDD and Temperature on static and dynamic behavior of CMOS Inverter.
• Design and simulation of 8:1 MUX modeled in VHDL and VERILOG, and synthesis on FPGA.
• Comparison of transient response of dynamic NAND2 and dynamic NOR2 gates.
• Design and simulation of 8-bit synchronous counter with LOAD, RESET, and up/down controls, modeled in VHDL and VERILOG, and synthesis on FPGA.
• Layout design and characterization of master-slave DFF.
• Design and simulation of 8-bit parity checker/generator modeled in VHDL and VERILOG, and synthesis on FPGA.
• Layout design and characterization of NAND2 and NAND4 gates.
• Design and simulation of 8:3 priority encoder, modeled in VHDL and VERILOG, and synthesis on FPGA.
• Layout design and characterization of Transmission gate
• Design and simulation of 4-digit decade counter, modeled in VHDL and VERILOG, and synthesis on FPGA.
• Design and simulation of 4-bit combinational multiplier, modeled in VHDL and VERILOG, and synthesis on FPGA.
• Design and simulation of 4-bit sequential multiplier, modeled in VHDL and VERILOG, and synthesis on FPGA.
  

 

Second Semester - II

VD-612 HDLS and FPGAS

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Verilog : basic concepts- Lexical conventions, data types, system tasks and compiler directives. Modules and ports. Gate level modeling- gate types, various types of gate delay specifications. Data flow modeling- assignments, delays, expressions, operators, . Behavioral modeling- structured procedures, procedural assignments, timing controls, conditional statements, loops, sequential and parallel blocks, generate blocks. Tasks and functions.

FPGA Architectures and Technology. Historical background, channel type FPGA- Xilinx 3000 and Actel ACT2 family, structured programmable array logic, programming FPGAs, benchmarking of FPGAs. Recent developments- new architectures such as Altera FLEX, Pilkington ( Motorola/ Toshiba), Xilinix XC4000, field programmable interconnect.

VHDL Synthesis for FPGA Implementation.: Mapping of statements to gate- assignment statements, logical, arithmetic and relational operators, vectors and slices, IF, Process, Case, Loop, Null, Wait statements. Modeling of flip-flops and latches. Modeling of FSM for synthesis. Some examples of synthesizable constructs.

Verilog Synthesis for FPGA Implementation: Verilog constructs and operators, interpretation of Verilog constructs, synthesis design flow- RTL to gates, translation, un-optimized  intermediate representations, logic optimization, technology mapping and optimization, technology library, design constraints, optimized gate level description.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-614 Analog Ic Design

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Integrated CMOS Amplifiers: Why integrated CMOS, single stage amplifiers-common source amplifiers with different types of loads, source follower, common gate amplifiers, cascade stage, choice of device models, Differential amplifiers-analysis of single ended and differential output amplifiers, common mode response, differential pair with MOS load, gilbert cells.

Current Mirrors: Basic current mirriors, cascade current mirriors, analysis of current mirrors, Frequency response of amplifiers: general considerations, frequency response of different types of amplifiers, Sources of Noise in CMOS Amplifiers: types of noise, representation of noise, noise in amplifiers.

CMOS Band gap References: supply independent biasing, temperature independent references, PTAT current generation , constant Gm biasing , speed and noise issues, Comparators.

Feedback in Amplifiers: feedback topologies, effect of loading, effect of feedback on noise, CMOS Operational Amplifiersperformance parameters, one-stage and two-stage Op Amps, gain boosting, input range limitations, slew rate.

Switched Capacitor Circuits: sampling switches, speed and precision considerations, switched capacitor amplifier –unity gain buffer, switched capacitor common mode feedback, switched capacitor filters.

CMOS Phase Lacked Loops: simple PLLs, charge pump PLLs, non ideal effects in PLLs, applications in frequency multiplication, skew and jitter reduction.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-616 Digital Signal Processing and DSP Architectures

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Implementations of Basic DSP Operations -Adders, Multipliers, Dividers; Discrete Fourier Transform Implementationcharacteristics of DFT- direct implementation of DFT, fast fourier transforms; Fixed-Point versus Floating-Point Operations; Pipelining and Parallelism; Re-timing, Unfolding- algorithm, properties and applications of unfolding, Folding- folding transformation, register minimization in folded architectures, folding of multirate systems.

Systolic/Array Architectures-implementation of array processors, algorithmic representations, Mapping methods-mapping without changing the number of nodes and with reduced number of nodes, projection method, multiprojection, partitioning, projection of nodes with different operations; Programmable DSP Architectures-the architecture of standard computer, architectural approaches for DSP processors, characteristics of available DSPs, FIR filter program, DFT program, instruction pipelining, special arithmetic modules, on-chip memory; Memory Structures and Addressing.

Multiplier and Multiplier accumulator – Modified Bus Structures and Memory access in P-DSP’s – Multiple access memory – Multi – port memory – VLIW architecture – pipelining – Special Addressing modes in P-DSP’s – On Chip Peripherals.

TMS320C3X PROCESSOR :Architecture –Data formats – Addressing modes – Groups of addressing modes – Instruction sets – Operation – Block diagram of DSP starter kit – Application, Programs for processing real time systems – Generating and finding the sum of series, Convolution of two sequences , Filter design.

ADSP PROCESSORS :Architecture of ADSP-21XX and ADSP – 210XX series of DSP processors – Addressing modes and Assembly language instructions – Applications programs – Filter design, FFT calculation- Blackfin DSP Processor.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

Practicals

VD-618 Analog Design Lab

Laboratory Experiments:

• Design and simulation of CS, CG and CD amplifier.
• Design of a p-n junction, BJT and MOSFET using different process parameters.
• Design and simulation of MOSFET based basic and cascade current mirrors.
• Study of dependence of SPICE parameters on process parameters for BJT.
• Design and simulation of a differential MOSFET Amplifier.
• Study of dependence of SPICE parameters on process parameters for a MOSFET.
• Design and simulation of a single stage CMOS operational amplifier.
• Layout design and simulation of a differential amplifier.
• Design and simulation of positive TC and negative TC band gap reference.
• Layout design and simulation of positive TC band gap reference.
• Design and simulation of a second order switched capacitor filter.
• Study of effect of short channel on SPICE parameters of a MOSFET.
• Design and simulation of simple phase locked loop.
• Design and simulation of charge pump phase locked loop.
• Comparison of different device models using SPICE

 

Semester - III

VD-621 Digital System Testing & Testable Design

Internal Assessment/Evaluation: 40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Combinational ATPG. Current sensing based testing. Classification of sequential ATPG methods. Fault collapsing and simulation.

Universal test sets. Pseudo-exhaustive and iterative logic array testing. Clocking schemes for delay fault testing. Testability classifications for path delay faults. Test generation and fault simulation for path and gate delay faults.

CMOS testing: Testing of static and dynamic circuits. Fault diagnosis: Fault models for diagnosis, Cause-effect diagnosis, Effectcause diagnosis.

Design for testability: Scan design, Partial scan, use of scan chains, boundary scan, DFT for other test objectives.

Built-in self-test: Estimation of test length, Test points to improve testability, Analysis of aliasing in linear compression, BIST methodologies, BIST for delay fault testing.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-623 Optimization Techniques

Internal Assessment/Evaluation:40 Marks

External Examination: 60 Marks

Duration of Examination: 03 Hours

Artificial Neural Networks (ANN): Objectives-History-Biological inspiration, Neuron model, Single input neuron, Multiinput neuron, Network architecture, Single layer of neurons, Multi-layers of Neurons.

Perceptron: Perceptron architecture, Stingle-neuron perceptron, Multi-neuron perceptron- Perceptron Learning Rule, Constructing learning rules, Training multiple neuron perceptrons.

Associative Learning: Simple associative network, Unsupervised Hebbrule- Hebb rule with decay, Instar rule, Kohonen rule.

Widro-Hoff Learning: Adaline Network, Single Adaline, Mean square Error, LMS algorithm, Analysis of Convergence.

Applications for VLSI Design: Applications of Artificial Neural Networks to Function Approximation, Regression, Time Series and Forecasting.

Genetic Algorithms (GA): Introduction, robustness of traditional optimization and search methods, goals of optimization, difference between genetic algorithms and traditional methods, a simple genetic algorithm, hand simulation, Grist for the search mill, similarity templates, learning the lingo.

GA Mathematical Foundations: Foundation theorem, schema processing, the two armed and k-armed bandit problem, schemata processing, building block hypothesis, minimal deceptive problem (MDP), extended schema analysis, MDP results, similarity templates as hyper planes.

GA Computer Implementation: Introduction, data structures, reproduction, crossover and mutation, a time to reproduce  and a time to cross, main program and results, mapping objective functions to fitness form, fitness scaling, codings, a multiparameter mapped fixed point coding, discretization, constraints.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD- 625 Seminar

Internal Assessment/Evaluation: 50 Marks

The student is required to deliver a seminar on some emerging topics of Manufacturing Systems Engineering. Senior faculty will supervise the students in selecting and preparation of the same. The student will submit two copies of seminar report and shall make oral presentation as per time schedule decided by the faculty concerned. Internal Evaluation will be made on the basis of report, presentation and the discussion during the presentation.

 

Semester - IV

VD– 628 Dissertation

Internal Assessment/Evaluation: 150 Marks

External Examination: 250 Marks

The complete dissertation work shall comprise of literature survey; problem formulation; methodology used; S/W; H/W tools used; Results and discussion followed by the conclusions & further scope of work in that area. The submission of dissertation in 6th semester shall be allowed only after ensuring that the research work carried out by the candidate has attained the level of satisfaction of the ‘Dissertation Supervisor (s)’ and proof of communication/acceptance of the research paper (if any; and certified in the report) in the relevant refereed journal/ conference.

The final dissertation external examination in 6th semester shall be taken by a panel of examiners comprising of concerned Supervisor (s); one external examiner (from the relevant field) nominated/approved by the competent authority. Hard copies of dissertation; one for each supervisor (s); examiner and the university/ department; are required to be submitted by the student before the final dissertation external examination. The candidate shall appear before the examining committee for oral examination and presentation on the scheduled date.

 

Details of Electives

VD-711 (Elective-I) Asynchronous System Design

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Fundamentals: Handshake protocols, Muller C-element, Muller pipeline, Circuit  implementation styles, theory. Static data-flow structures: Pipelines and rings, Building blocks, examples.

Performance: A quantitative view of performance, quantifying performance, Dependency graphic analysis. Handshake circuit implementation: Fork, join, and merge, Functional blocks, mutual exclusion, arbitration and metastability.

Speed-independent control circuits: Signal Transition graphs, Basic Synthesis Procedure, Implementation using state-holding gates, Summary of the synthesis Process, Design examples using Petrify. Advanced 4-phase bundled data protocols and circuits: Channels and protocols, Static type checking, More advanced latch control circuits.

High-level languages and tools: Concurrency and message passing in CSP, Tangram program examples, Tangram syntaxdirected compilation, Martin’s translation process, Using VHDL for Asynchronous Design. An Introduction to Balsa: Basic concepts, Tool set and design flow, Ancillary Balsa Tools

The Balsa language: Data types, Control flow and commands, Binary/Unary operators, Program structure. Building library Components: Parameterized descriptions, Recursive definitions. A simple DMA controller: Global Registers, Channel Registers, DMA control structure, The Balsa description.

Principles of Asynchronous Circuit Design - Jens Sparso, Steve Furber, Kluver Academic Publishers.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-713 (Elective-I) Low-Power VLSI Design

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Introduction: Sources of power dissipation, important parameters for low power design, Low power design approaches.

Transistor sizing vs. dissipation and speed, effect of scaling, Process Technology and Integration-Low power CMOS/BiCMOS Process, Low power SOI CMOS, Low Power Lateral BJT on SOI, LVLP CMOS Transistor structure via Poly profile Engineering.

Low power circuit techniques: Flip flops and Latches, Logic, High Capacitance Nodes. Energy Recovery CMOS: Retractile Logic, Reversible pipelines, High performance approaches.

Low power clock distribution: Power Distribution in Clock Distribution, Single driver vs. Distributed buffers, Buffer and device sizing, Zero skew vs. tolerant Skew, Chip and package Co-design of Clock Network.

Logic synthesis for low power: Power estimation Techniques, Power Minimization Techniques.

Design of low power arithmetic and memory elements: Circuit Design Style, Design of circuits for addition, Multiplication, Division.

Low power microprocessor Design – system power management, architectural trade-offs, choosing supply voltage, low power clocking, implementation options for low power.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-715 (Elective-I) Memory Design and Testing

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Introduction to Semiconductor Memories and Technologies: Internal organization of memory chips, basic memory elements, memory types, trends in SRAM and DRAM design, Non-volatile memory technologies.

SRAM and DRAM Cell Design; basic structures-NMOS static/dynamic circuits, CMOS circuits, cell design.

Sense Amplifiers: Voltage and Current Sense Amplifiers; Reference Voltage Generation; Voltage Converters.

Cache Memory Design.: concept of locality in space and time, interfacing cache memory with CPU, associated problemsparasitic capacitances, critical timing paths, bus turnaround.

Memory Testing: Reliability-failure mechanisms for memories, reliability modeling and fault detection, Yield, Radiation Effectsradiation types effecting the memory, radiation hardening techniques.

Memory chip design: a case study

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-721 (Elective-II) Mixed-Signal Ic Design 

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Data Converters: Introduction, Characteristic Parameters, Basic DAC and ADC Architectures.

Sampling and Aliasing, SPICE models for DACs and ADCs, Quantization Noise Data Converter SNR: Clock Jitter, Improving SNR using Averaging, decimating filters for ADC’s, Interpolating filters for DAC’s, Band pass and high pass Sinc filters, using feedback to improve SNR.

Noise Shaping data converters: SPICE model, First order noise shaping, First order Noise Shaping, - Digital first order NS Modulators, Modulation Noise,Decimating and filtering the output of a NS Modulator,Analog Sync filter using SPICE,Analog Implementation of First order NS Modulator, Feedback DAC,Effect of parameters of Integrator, Forward modulator, op-amp. Second order Noise Shaping, Noise shaping Topologies.

Implementing data converters: R-2R topologies for DAC’s – Current mode,voltage mode, wide swing current mode DAC, topologies without an op-amp,effects of op-amp parameters. Implementing ADC’s- Implementing S/H,Cyclic ADC, Pipeline ADCusing 1.5 bits per stage, capacitor error averaging,comparator placement, clock generation, offsets and alternative topologies, Layout of Pipelined ADC’s.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-723 (Elective-II) Advanced Computer Architecture

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Multiprocessors and multi-computers. Multi-vector and SIMD computers. PRAM and VLSI Models. Conditions of parallelism. Program partitioning and scheduling. Program flow mechanisms. Parallel processing applications. Speed up performance law.

Advanced processor technology. Superscalar and vector processors. Memory hierarchy technology. Virtual memory technology. Cache memory organization. Shared memory organization.

Linear pipeline processors. Non linear pipeline processors. Instruction pipeline design. Arithmetic design. Superscalar and super pipeline design. Multiprocessor system interconnects. Message passing mechanisms.

Vector Processing principle. Multivector multiprocessors. .Compound Vector processing. Principles of multithreading. Fine grain multicomputers. Scalable and multithread architectures. Dataflow and hybrid architectures.

Parallel programming models. Parallel languages and compilers. Parallel programming environments. Synchronization and multiprocessing modes. Message passing program development. Mapping programs onto multicomputers. Multiprocessor UNIX design goals.

MACH/OS kernel architecture. OSF/1 architecture and applications.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-725 (Elective-II) Neural Networks

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Introduction: History, overview of biological Neuro-System, Mathematical Models of Neurons, ANN architecture, Learning rules, Learning Paradigms-Supervised, Unsupervised and reinforcement Learning.

Supervised Learning and Neurodynamics: Perceptron training rules, Delta, Back propagation training algorithm, Hopfield Networks, Associative Memories.

Unsupervised and Hybrid Learning: Principal Component Analysis, Self-organizing Feature Maps, ART networks, LVQ, Applications for VLSI Design.

Applications of Artificial Neural Networks to Function Approximation, Regression, Classification, Blind Source Separation, Time Series and Forecasting.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-712 (Elective-III) RF Integrated Circuits

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Active RF Components and their characteristic parameters:RF diodes, BJT, FET, HEMT.

RF Filter Design: Filter configurations, resonators, filter realizations – Butterworth, Chebychev.

High-Frequency Amplifier Design: Zeros as bandwidth enhancer, shunt series amplifier, bandwidth enhancement with fT doublers, voltage references and biasing, tuned and cascaded amplifiers, RF Power Amplifier Design.

Noise in RF Circuits: types of noise, two port noise theory, Low-Noise Amplifier (LNA) – intrinsic MOSFET two port noise parameters, LNA topologies, design example, LNA Design example.

Phase-Locked Loops: PLL models, noise properties, sequential phase detectors, loop filters and charge pumps. RF Oscillators: tuned and negative resistance oscillators. Mixers: non-linear systems as mixers, multiplier based mixers.

RF amplifier design – a case study

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-714 (Elective-III) Advanced Computational Methods

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Solution of two or more nonlinear equations by iterative methods (Picard and Newton’s methods) Spline interpolation, cubic splines, Chebyshev polynomials, Minimax approximation.

Eigenvalues and vectors of a real symmetric matrix – Jacobi method. Eigenvalue problem for ordinary differential equations.

Numerical solution of a parabolic equation. Explicit method, simple implicit method and Crank-Nicholson method. Stability.

Numerical Solution of elliptic problems. Dirichlet and Neumann problems (Cartesian and Polar coordinates)

Numerical solution of hyperbolic equations. Explicit method. Method of characteristics. Stability.

The finite element method – Ritz, collocation and Galerkin methods. Boundary value problems for ordinary differential equations. Shape functions. Assembly of element equations.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-716 (Elective-III) FPGA - Based System Design

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Multirate signal processing- Decimation and Interpolation. Spectrum of decimated and interpolated signals, Polyphase decomposition of FIR filters and its applications to multirate DSP. Sampling rate converters, Sub-band encoder.

Filter banks-uniform filter bank. direct and DFT approaches. Introduction to ADSL Modem. Discrete multitone modulation and its realization using DFT. QMF. Short time Fourier Transform Computation of DWT using filter banks. Implementation and verification on FPGAs.

DDFS- ROM LUT approach. Spurious signals, jitter. Computation of special functions using CORDIC. Vector and rotation mode of CORDIC. CORDIC architectures. Implementation and verification on FPGAs.

Block diagram of a software radio. Digital downconverters and demodulators Universal modulator and demodulator using CORDIC. Incoherent demodulation - digital approach for I and Q generation, special sampling schemes. CIC filters. Residue number system and high speed filters using RNS. Down conversion using discrete Hilbert transform. Undersampling receivers, Coherent demodulation schemes.

peech coding- speech apparatus. Models of vocal tract. Speech coding using linear prediction. CELP coder. An overview of waveform coding. Vocoders. Vocoder attributes. Block diagrams of encoders and decoders of G723.1, G726, G727, G728 and G729.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-722 (Elective-IV) Micro Electro Mechanical Systems

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Historical Background: Silicon Pressure sensors, Micromachining, MicroElectroMechanical Systems. Microfabrication and Micromachining : Integrated Circuit Processes, Bulk Micromachining : Isotropic Etching and Anisotropic Etching, Wafer Bonding, High Aspect-Ratio Processes (LIGA) Physical Microsensors: Classification of physical sensors, Integrated, Intelligent, or Smart sensors, Sensor Principles and Examples: Thermal sensors, Electrical Sensors, Mechanical Sensors, Chemical and Biosensors. Microactuators: Electromagnetic and Thermal microactuation, Mechanical design of microactuators, Microactuator examples,

microvalves, micropumps, micromotors Microactuator systems : Success Stories, Ink-Jet printer heads, Micro-mirror TV Projector. Surface Micromaching : One or two sacrificial layer processes, Surface micromachining requirements, Polysilicon surface micromachining, Other compatible materials, Silicon Dioxide, Silicon, Micromotors, Gear trains, Mechanisms. Application Areas: All- mechanical miniature devices, 3-D electromagnetic actuators and sensors, RF/Electronics devices, Optical/Photonic devices, Mecical devices e.g DNA chip, micro-arrays. Lab/Design: (two groups will work on one of the following design project as a part of the course) RF/Electronics device/system, Optical/Photonic device/system, Medical device e.g. DNA-chip, microarrays.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-724 (Elective-IV) VLSI for Wireless Communication

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Review of Modulation Schemes – BFSK- BPSK –QPSK – OQPSK – Classical Channel - Additive White Gaussian Noise – Finite Channel Bandwidth - Wireless Channel- Path Environment - Path Loss – Friis Equation – Multipath Fading – Channel Model.

Envelope Fading – Frequency Selective Fading – Fast Fading - Comparison of different types of Fading- Review of Spread Spectrum – DSSS – FHSS - Basic Principle of DSSS - Modulation –Demodulation - Performance in the presence of noisenarrowband and wideband interferences.

Receiver Front End – Motivations - General Design Philosophy- Heterodyne and Other architectures – Filter Design – Band Selection Filter – Image Rejection Filter - Channel Filter - Non idealities and Design Parameters - Harmonic Distortion – Intermodulation -Cascaded Nonlinear Stages – Gain Compression – Blocking – Noise – Noise Sources -Noise Figure - Design of Front end parameter for DECT.

Low Noise Amplifier – Introduction - Matching Networks – Matching for Noise and Stability – Matching for Power – Implementation - Comparison of Narrowband and Wideband LNA - Wideband LNA Design - Narrowband LNA –Impedance matching -Power matching- Salient features of LNA –Core Amplifier Design.

Demodulators - Delta Modulators - Low Pass Sigma Delta Modulators – High Order Modulators - One Bit DAC and ADC –Passive Low Pass Sigma Delta Modulator - Band pass Sigma Delta Modulators – Comparison – PLL based Frequency Synthesizer – Loop Filter Design and Implementation.

Implementations: VLSI architecture for Multitier Wireless System - Hardware Design Issues for a Next generation CDMA System - Efficient VLSI Architecture for Base Band Signal processing.

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.

 

VD-726 (Elective-IV) Research Methodology

Internal Assessment/Evaluation: 30 Marks

External Examination: 45 Marks

Duration of Examination: 03 Hours

Introduction to Educational Research :Concept, types – basic, applied and action, Need for educational research; Reviewing Literature:Need, Sources – Primary and Secondary, Purposes of Review, Scope of Review, steps in conducting review.

Identifying and defining research problem: Locating, analysing stating and evaluating problem. Generating different types of hypotheses and evaluating them.

Methods of Research :Descriptive research design - survey, case study, content analysis, Ex-post Facto Research, Correlational and Experimental Research.

Sampling Techniques:Concept of population and sample’ sampling techniques - simple random sampling, stratified random sampling, systematic sampling and cluster sampling, snow ball sampling, purposive sampling, quota sampling techniques. determining size of sample.

Design and development of measuring instruments, Tests, questionnaires, checklists, observation schedules, evaluating research instruments, selecting a standardized test Procedure of data collection: Aspects of data collection, coding data for analysis.

Statistical Methods of Analysis :Descriptive statistics: Meaning, graphical representations, mean, range and standard deviation, characteristics and uses of normal curve. Inferential statistics: t-test, Chi-square tests, correlation (rank difference and product moment), ANOVA (one way), Selecting appropriate methods. Procedure for writing a research proposal:Purpose, types and components of research proposal. Procedure for writing a research report:Audiences and types of research reports, Format of research report and journal articles. Strategies for evaluating, Research disseminating and utilising research – An Overview.

Practice Tasks

• Define a research problem in engineering education/industry after studying problem situation and literature
• Given the purpose, objectives of research, write hypotheses
• Select research designs for the given research objectives
• Identify the measuring instruments for the given research objectives/hypotheses
• Identify the appropriate statistical methods of analysis for the given research proposal.
• Critically analyse the given research reports on various aspects such as hypothesis, design, measuring tools, statistical analysis, interpretation etc. to identify the gaps or weaknesses in the study.
  

Note: The examiner is required to set Eight questions in all carrying equal marks covering the entire syllabus. The candidate is required to attempt Five questions.