Vel Tech Rangarajan Dr. Sagunthala R and D Institute of Science and Technology Courses

M.Tech. (VLSI Technology)

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Duration: 2 Years

Eligibility: B.Tech/ B.E.

Course Structure

Course Code	Course Title
Semester  I
PCSA40	Advance Computer Architecture
PVLA27	Advanced High Speed Digital System Design
PVLA28	VLSI Designing with VHDL
******	Elective I
******	Elective II
Practical
PVLA2	VHDL Lab
PVLA30	Digital System Design Lab
Semester  II
PVLA31	CMOS Design Techniques
PVLA32	VLSI Chip Testing
PVLA33	VLSI Verification Methodologies
******	Elective III
******	Elective IV
Practical
PVLA34	VLSI Verification Lab
PVLA35	VLSI Testing Lab
Semester  III
******	Elective V
******	Elective VI
******	Seminar
Practical
PVLA48	Project Phase I
Semester  IV
PVLA36	Project Phase II
List of Electives
PVLA37	ASIC Design Issue
PVLA38	Verilog Programming
PVLA3	Computer Aided Design of VLSI Circuits
PVLA40	System on Chip Designing
PVLA41	Signal Processing in VLSI
PVLA42	DSP Processor Architecture
PVLA43	Analog Mixed VLSI Designing
PVLA44	Advanced Microcontrollers
PVLA45	Neural Networks and Applications
PVLA46	Memory Designing
PMAA04	Mathematical Foundations of Electronics Engineering
PVLA47	VLSI Basic & Concepts

Course Detail

Semester - I

PCSA40   Advanced Computer Architecture                                 

Unit - I

Computation model – The concept of Computer Architecture – Introduction to Parallel Processing.

Unit - II                                                                                     

Introduction to ILP Processing – Pipelined Processors – VLIW Architecture – Super Scalar Processors

Unit - III                                                                                                

Code Scheduling for ILP-processors – Introduction to Data Parallel Architecture – SIMD Architecture – MIMD Architecture.

Unit - IV                                                                                    

Vector Architecture – Multi threaded Architecture.

Unit - V

Distributed Memory MIMD Architecture – Shared memory MIMD Architecture.

 

PVLA27   Advanced and High Speed Digital System Design                                 

Unit - I

Overview of digital technology. Logic families : TTL and CMOS. Reading and Understanding data books.

Unit - II

Interfaces - Standard components – Programmable devices : PROM- PAL – PLA- PLD- CPLD – FPGA. HDL Programming (VHDL, Verilog).

Unit - III

Electrical Realities – Resistance , capacitance and inductance- Power dissipation and drops – Ringing, reflections, and terminations.

Unit - IV                                                                                              

Wire delays and time constraints – decoupling and signal integrity – Clock Distribution – computer aided design.

Unit - V           

Logic compilation. Two level and multi level logic synthesis – technology independent optimization – technology mapping – sequential logic synthesis – tools for mapping to PLDs and FPGAs.

 

PVLA28   VLSI Designing With VHDL                                                           

Unit - I

Advantages and features of VHDL – VHDL design Flow- Basic terminologies of VHDL – Entity declaration – Architecture (structural , dataflow, behavioral) – Configuration declaration – package declaration . VHDL Elements: Identifiers – Data objects – data types – operators.

Unit - II

Behavioral Modeling: Entity declaration – Architecture body – process statement- assignment statement: variable , signal – wait – if else – case – Null – loop statements. Delay model – signal drivers – generics – sequential multiple process – passive process.

Unit - III

Dataflow Modeling : Concurrent statement – conditional – block statement. Structural modeling : component declaration and instantion.

Unit - IV

Subprograms : Function – resolution function – procedure. Packages: Package declaration – package body. Attributes : Value – function kind – signal kind . Configurations : Default configuration – component configuration.

Unit - V

Overloading : subprogram overloading – operator overloading. Generate statement. State Machine Modeling : Moore SM, Mealy SM, Generic priority encoder – state machine coding styles – guidelines for FSM coding.

 

PVLA2 - VHDL Lab                                                                 

• Modeling of sequential digital system using VHDL
• Modeling of sequential digital system using VERILOG
• Design and implementation of ALU using FPGA
• Simulation of N-MOS and CMOS circuits using Pspice
• Modeling of MOSFET using ‘c’
• Implementation of FFT digital filter in digital (DSP) processor.
• Implementation of MAC unit using FPGA
• Implementation of DSP algorithm using Software package.
• Implementation of Linear and circular convolution of DSP processor.

 

PVLA30   Digital System Design Lab                      

• Logic analyzer and oscilloscope basics
• Timing, state, capture, bandwidth
• Glitches and transient events
• Debugging techniques
• System-level components
• Static, dynamic, and nonvolatile memories
• RAM, ROM, PROM, EPROM, EEPROM
• Memory controllers and timing
• Serial and parallel protocols
• Synchronous vs asynchronous data communicate.

 

Semester - II

PVLA31   CMOS Design Techniques

Unit - I                                                                                                

Introduction to the MOS technology and fabrication process flow-CMOS combinational logic design.

Unit - II                                                                                                                                                   

Design of basic gates transmission gates and complex logic.

Unit - III

Device sizing - timing parameters and estimation of layout resistance and capacitance-Design rules for CMOS layout.

Unit - IV                                                                                                          

Introduction to layout and simulation tools-Place and root-Extraction, LVS.

Unit - V

Netlist to GDS-II flow-Device generator, libraries.

 

PVLA32    VLSI Chip Testing 

Unit - I                                                                                                

Fault modeling-Automatic test pattern generation.

Unit - II

Fault simulation-Testability measurements-Combinational circuit test generation-Sequential circuit test generation.

Unit – III

Design for testability and scan test.

Unit - IV                                                                                  

Built-in self testing-Boundary scan testing.

Unit - V

Memory testing-analog and mixed signal test-delay test-IDDQ test –case study.

 

 PVLA33    VLSI Verification Methodologies                       

Unit - I

Introduction to verification –Types of verification

Unit - II

Code coverage-introduction to system verilog,task and functions in system verilog.

Unit - III

OOPS terminology-Implementation of OOPS concepts in system verilog.

Unit - IV                      

Andomization-case studies

Unit - V

Assertions property and time-Functional coverage.

 

PVLA34    VLSI Verification Lab                                                       

• Introduction to layout design rules.
• Layout of basic logic and combinational circuits
• Logic verification principles.
• Analog circuit verification using cadence tools.
• Verification of layouts(DRC,LVS)
• SPICE simulation and coding.

Tools Used: Cadence tools, mentor graphics tools

PVLA35   VLSI Testing Lab                                                              

• VLSI testing process.
• Test generation for sequential circuit.
• Testing of combinational circuit.
• Defect based testing, boundary scan, DFT, BIST.
• Mixed signal testing.
• ALU design and testing example in FPGA board.

 

List of Electives

PVLA37   Asic Design Issue                                                                             

Unit - I

Introduction to ASIC, CMOS Logic and ASIC Library Design, Types of ASCIs – Design Flow- CMOS Transistors, CMOS Design Rules – Combinational logic cell – Sequential Logic cell – Data Path logic cell – Transistors as Resistors – Transistors Parasitic Capacitance – Logical effort – Library Cell design – Library Architecture

Unit - II

Programmable ASICs, Programmable ASICs Logic cells and Programmable ASCI Input Output Cells Anti fuse- Static RAM – EPROM and EEPROM technology – PREP Benchamrks – Actel ACT – Xilinx LCA – Altera FLEX – Altera MAX  DC & AC Inputs & Outputs –Clock & power inputs – Xilinx Input / Output Blocks.

Unit - III

Programmable ASIC Interconnect, Programmable ASIC Design Software and low level design entry Actel ACT – Xilinx LCA – Xilinx EPLD – Altera MAX 5000 & 7000 – Altera MAX 000 – Altera FLEX  - Design Systems – Logic synthesis – Half gate ASIC- Schematic entry – Lowlevel design language – PLA tools – EDIF – CFI Design representation.

Unit - IV

ASIC Construction, Floorplanning, Placement and Routing system partition – FPGA Partitioning – Partitioning methods – Floorplanning – Placement – Physical Design Flow – Global Routing – Detailed Routing – Special Routing – Circuit Extraction – DRC

Unit - V                                   

Review of VHDL / VERILOG: Entities and Architectures, Design using Xilinx family FPGA

 

PVLA38    Verilog Programming                                                              

Unit - I

Introduction to verilog – History – Getting Started to Verilog

Unit - II

System Tasks and functions – Procedural assignment its type – Initial and Always statements -“Begin – End” and “fork – Join” blocks- “Wait “ statement

Unit - III

Nonblocked  assignment – Procedural flow control – loops

Unit - IV

Blocking and Nonblocking assignments guidelines – Determinism – Non determinism and Race condition – Stratified event queue – parameters

Unit - V

Compiler Derivatives – FSM Modelling – Task and functions – Text I/O – defparam and its example – Introduction to switch level modeling – UDPS – PLI overview

 

PVLA3   Computer Aided Design For VLSI Circuits                               

Unit - I

Introduction to VLSI Methodologies – VLSI Physical design automation – Design and fabrication of VLSI devices – Fabrication process and its impacet of Physical design.

Unit - II

A quick tour of VLSI design Automation tools – Data structure and basic algorithms – Algorithmic Graph theory and computational complexity – Traceable and intraceable problems

Unit - III

General purpose methods for combinational optimization – Partitioning – Floorplanning and PIN assignment – Placement – Routing

Unit - IV

Stimulation – Logical synthesis – Verification – High level synthesis – Compaction .

Unit - V

Physical design automation of  FPGA , MCMS – VHDL – Verilog – Implementation of simple circuits using VHDL and Verilog.

 

PVLA40     System On Chip Designing                                                                

Unit - I

System On Chip Technology challenges , System On a Chip (SOC) components, SOC Design methodology

Unit - II

Parameterized systems – on – a-Chip, System – on – a – Chip pheripheral cores, SOC and Interconnect centric architectures

Unit - III

System level design representations and modeling languages , Target archgitecture models, Intra – chip communication , Graph partitioning algorithms.

Unit - IV

Task time measurements , Interconnect latency modeling, Back annotation of lower level timing to high – level models, Synthesis of  Soc components

Unit - V

System level , Block level and Hardware / Software Co-verification, SOC components: Emulation, Co-Simulation, Physical Verification.

 

PVLA41    Signal Processing In VLSI                                                

Unit - I 

Multirate Signal Processing – Introduction sampling and signal reconstruction- Sampling rate convention – Decimation by an integer factor- Interpolation by an integer factor- Sampling rate convention by rational factor- Sample rate convertors as a time variant system – Practical structure of decimators and interpolator – Direct form and polyphase FIR Structures with Time varying coefficients.

Unit - II

Multirated FIR filter design – Design of FIR filters of sampling rate convention – Multistage implementation of Sampling rate convention – Application of interpolation and decimation in signal processing operations low pass and bandpass filters – Filter band implementation – Sub band processing – Decimated filter bands – Two channel filter bands – Uniform DFT Filter bands

Unit - III

Power spectral estimation of spectra from finite duration observations of a signal – The periodogram – Use of DFT in power spectral estimation – Non periodical methods for power spectral estimation – Barlett Wech and Blackman – tukey methods – Comparison of performance of non periodic power spectral estimation methods.

Unit - IV

Periodic method of spectral estimation – relationship between Auto correlation and model parameters – Autoregressive process and linear production, Yule – Walker .

Unit - V

Burg and Non consisted least Square methods – Sequential estimation – Moving Average and ARMA models – Minimum variance method – Pizaenko’s harmonic decomposition method – Music method

 

PVLA42    DSP Processor Architecture       

Unit - I

Fundamentals of programmable DSPs – Multiplier and Multiplier accumulator – Modified Bus Structures and memory access in P -DSP’s – Multiple access memory – Multi port memory – VLIW architecture – Pipelining – Special Addressing modes in P –DSP’s – On Chip Pheripherals

Unit - II

Tms 320c5X Processor – Architecture – Addressing modes – Assembly language Instructions – Pipeline structure and Operation – Block diagram of DSP Starter Kit – Application programs for Processing real time signals

Unit - III

Tms 320c3X Processor- Architecture – Data format – Addressing modes –Groups of Addressing modes – Instuction sets and operations - Block diagram of DSP Starter Kit – Application programs for Processing real time signals – Genearting andfinding the sumof series – Convolution of Two sequence – Filter Design

Unit - IV

ADSP Processors – Architecture of ADSP (21XX ) and ADSP( 210XX) series of DSP Processors – Addressing modes – Assembly language instructions –Application program filter design – FFT calculation

Unit - V

Advanced Processors architecture of TMS320c54X –Pipeline operation code composer studio – Architecture of TMS320c6X – Architecture of Motorola DSP563XX – Comparison of the futures of DSP Assembly processors.

 

PVLA43   Analog Mixed VLSI Designing                                                      

Unit - I

Basic CMOS Circuit Techniques, Continuous Time Low Voltage signal processing ; Mixed Signal VLSI chips – Basic CMOS Circuits – Basic Gain stage – Gain Boosting techniques – Super MOS Transistors – Primitive analog cells – Linear voltage – current converters – MOS multipliers and Resistors – CMOS , Bipolar and Low voltage BiCMOS Opamp design- Instrumentation amplifier design – Low voltage filters

Unit - II

Basic BiCMOS circuit techniques , Current – model signal processing – Continuous , Time signal processing – Sampled data signal processing – Switched – current data convertors

Unit - III

Sampled data – analog filters – over sampled A/D converters and analog integrated sensors – First and Second order SC Circuits – Bilinear transformation – cascade design – Switched capacitor ladder filter – Synthesis of switched – current filters – Nyquist rate A/D converters – modulators for over sampled A/D conventions.- First and second order and multibit sigma - delta modulators- Interpolative modulators – cascade architecture – Decimation Filters – Mechanical , Thermal, Humidity and Magnetic Sensors – Sensor Interfaces

Unit - IV

Analog VLSI Interconnect in VLSI – Scaling of Interconnect – a Model for estimating wiring density – A configurable architecture for prototype analog circuits

Unit - V

Statistical modeling and stimulation – Analog computer – Aided Design – Analog and Mixed analog – Digital layout – Overview of Statistical concepts – Statistical device modelling – Statistical circuit simulation – Automation analog circuit design  - Automatic Analog layout – CMOs Transistor layout – Resistor layout – Capacitor layout – Analog Cell layout – Mixed analog – Digital layout

 

PVLA44    Advanced Microcontroller         

Unit - I

Microprocessor architecture – Instruction set – Data formats – Instruction formats – Addressing modes – memory hierarchy – register file – Cache – Virtual memory and paging – Segmentation – Pipelining – Instruction Pipelining – Pipelining Hazards – Instruction level parallelism – Reduced Instruction set – Computer principles- RISC versus CISC – RISC Properties and evaluation – ON Chip Register files versus Cache Evaluation

Unit - II

High performance CISC architecture – Pentium – Software model – Functional description – CPU PIN description – RISC Concepts – BUS Operation – Super scalar architecture – pipeling – Branch prediction – Instruction and Caches  - Floating point unit – Protected mode operation – Segmentation – paging – protection – Multitasking – Expressions and Interrupts I/O –Virtual 8086 model  = Interrupt Processing – Instruction types – Address modes – Processor flags – Instruction sets – Programming the Pentium processor

Unit - III

Arm Architecture . Language program , Organisation and implementation , Instruction set , Thumb Instruction set – ARM CPU cores.

Unit - IV

Motorola 68HC11 Microcontrollers – Instructions – Addressing modes – Operating  modes – Hardware reset – Interrupt system – Parallel I/O ports- Flags-real time clock-programmable timer-pulse accumulator-serial communication interface-AtoD converter-hardware expansion-assembly language programming.

Unit - V

  CPU architecture-Instruction set-interrupts-Timers-IO port-I2C bus for pheripheral chips-A/D converter-UART.

 

PVLA45    Neural Networks and Applications                               

Unit - I

Introduction to artificial neural networks-Nero-physiology-general processing element-ADALINE-LMS learning rule-MADALINE-MR2 training algorithm

Unit - II

Back propagation network-updating of outputs and hidden layers weights-applications of BPN-associative memory-bidirectional associative memory- Hopfield memory-traveling sales man problem

Unit - III

Simulated annealing and CPN- Annealing – Boltzman machine – Learning – Appliactions –Counter Propagation network architecture – Training – Application

Unit - IV

Self Organised map – learning algorithm – Feature map classifier – Application – Architecture of adaptive resonance theory – Pattern matching in ART network

Unit - V

Architecture of Neocognitron – Data Processing and Performance of architecture of Spacio – temporal networks for speech recognition.

 

PVLA46    Memory Designing                                                                      

Unit - I

Static RAM Structure – CMOS SRAM Architecture – MOS SRAM Cell and Peripheral Circuit architecture – Bipolar SRAM Technologies – Silicon on Insulator technology – Advanced SRAM architecture and technologies – application specific SRAM’s

Unit - II

DRAM Technology development – CMOS DRAM – DRAM Cell theory and advanced cell structures – BiCMOS DRAM – Soft error failures in DRAM – Advance d DRAM design and architecture – application specific DRAM – Non volatile memories-

Unit - III

Masked ROM – High design ROM – Programmable Read Only Memories – Bipolar PROM – CMOS PROM- EPROM – Floating gate EPROM – EEPROM – EEPROM Technology and architecture – Non volatile SRAM – Flash Memory – Advanced Flash Memory architecture

Unit - IV

Memory Fault modeling – Testing and memory design for testability and fault tolerance RAM – Fault Modelling – Electrically testing – Pseudo code- Random Testing – Mega bit DRAM Testing – Non Volatile Memory modelling and testing(IDDQ)-Fault modeling and testing – Application specific memory testing – Semiconductor memory reliability and radiation effects – General reliability issues – RAM Failure modes and mechanism – Non volatile memory reliability – Reliability modeling and failure rate reduction -  Design for reliability

Unit - V

Advanced Memory technologies and High density memory packaging  technologies – Ferroelectric Random Access Memories ( FRAMs) – Gallium Arsenide (GaAs) – FRAMs – Analog memories – Magnetoresistive Random Access memories (MRAMs) – Experimental memory devices- Memory hybrids and MCMs ( 2D)  - Memory Stacks and MCMs(3D) – Memory MCM Testing and reliability issues – Memory cards -  High density memory packaging future directions.

 

PMAA04    Mathematical Foundations Of Electronics Engineering                     

Unit – I

Fuzzy Logic 

Basic concepts of fuzzy logic – fuzzy sets – operations of fuzzy sets – properties of fuzzy sets – fuzzy relations – composition of fuzzy relations – fuzzy propositions – fuzzy quantifiers

Unit - II

Dynamic Programming                                                                                                

Bellman’s principle of optimality – solution of problem of with finite number of stages – backward recursion – applications of dynamic programming – characteristics of dynamic programming

Unit - III

Matrix Theory                                                                                                                  

Eigenvalues and eigenvectors of matrices – diagonalization of matrices – defective matrices - generalized eigenvectors – Jordan canonical form of matrices - pseudo-inverse of a matrix – least-square solutions of overdetermined linear systems – the method of normal equations

Unit - IV

One Dimensional Random Variables                                                                     

Random variables – probability distribution – moments – moment generating functions and their properties – binomial, Poisson, geometric, uniform, exponential, gamma and normal distributions – function of a random variable

Unit - V

Queueing Models                                                                                                                          

Basics of queueing models –Poisson queue systems – transient state probability – steady state probabilities – single and multi-server models with finite and infinite capacity – Little’s formula - (M-G-1) queueing model – Pollaczek-Khinchine formula

 

PVLA47    VLSI Basic & Concepts                                                                             

Unit - I

Introduction to CMOS circuits                                                                                   

MOS transistors, MOS switches, CMOS logic: Inverter, combinational logic, NAND, NOR gates, compound gates, Multiplexers. Memory: Latches and registers. Circuit and system representations: Behavioral, structural and physical representations.

Unit - II

MOS transistor theory                                                                                                  

 NMOS, PMOS enhancement mode transistors,  Threshold voltage, body effect, MOS device design equations, MOS models, small signal AC characteristics, CMOS inverter DC characteristics, static load MOS inverters, Bipolar devices - advanced MOS modeling – large signal and small signal modeling for BJT.

Unit - III

low – voltage low  power vlsi cmos circuit design  cmos invertor – Characteristics – Power dissipation. Capacitance estimation. CMOS static logic design, Logic styles.

Unit - IV

Circuit characterization and performance estimation                                    

Estimation of resistance, capacitance, inductance. Switching characteristics, CMOS gate transistor sizing, power dissipation, sizing routing conductors, charge sharing, Design margining yield, reliability. Scaling of MOS transistor  dimensions.

Unit - V

CMOS circuit and logic design                                                                                   

CMOS logic gate design,   physical design of simple logic gates. CMOS logic structures. Clocking strategies, I/O Structures.